| Title |
Phase Synchronization Operator for on-chip Brain Functional Connectivity Computation |
| Authors |
DELGADO RESTITUTO, MANUEL , DELGADO RESTITUTO, MANUEL , ROMAINE, JAMES BRIAN, RODRÍGUEZ VÁZEQUEZ, ÁNGEL , RODRÍGUEZ VÁZEQUEZ, ÁNGEL |
| External publication |
Si |
| Means |
IEEE Transactions on Biomedical Circuits and Systems |
| Scope |
Article |
| Nature |
Científica |
| JCR Quartile |
1 |
| SJR Quartile |
1 |
| JCR Impact |
4.042 |
| SJR Impact |
1.192 |
| Web |
http://doi.org/10.1109/tbcas.2019.2931799 |
| Publication date |
01/01/2019 |
| ISI |
000498642200018 |
| DOI |
10.1109/TBCAS.2019.2931799 |
| Abstract |
This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters, and adders. The processor, fabricated in a 0.18-$\\mu$m CMOS process, only occupies 0.05mm$<^>2$ and consumes 15nW from a 0.5V supply voltage at a signal input rate of 1024S/s. These low-area and low-power features make the proposed processor a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for assessing the patterns of correlated activity in neural assemblies through the evaluation of functional connectivity maps. |
| Keywords |
Functional connectivity; low power CMOS VLSI; neural signal processing; phase synchronization; seizure detection |
| Universidad Loyola members |
|
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